In the past, chipmakers like Intel Corp and Taiwan Semiconductor Manufacturing Co raced each other to make the features on chips smaller and smaller to cram more computing power onto a single chip.
But the newest race in chipmaking is to stack “chiplets” or “tiles” – tiny squares sliced out of what would normally be a single, larger chip – on top of a base layer of silicon in one package, mixing and matching different technologies rather than trying to make a single big chip.
What analysts call three-dimensional packaging saves costs. It also could help manufacturers improve chip performance even as they push the physical limits of how small chip features can get.
Intel on Monday outlined new three-dimensional packing technology, and analysts said it has a lead over its rivals in the field.
Intel believes the technology can help it win more packaging customers such as Amazon.com, which it announced Monday, even though parts of the chips used by such customers might still be made by Intel’s rivals.
“We’re not going to pack everything on one piece of silicon in the future,” said Kevin Krewell, principal analyst at TIRIAS Research.
WHAT IS THREE DIMENSIONAL CHIP PACKAGING?
To make a 3D chip, chipmakers slice chips into “tiles” or “chiplets” that are then stacked onto what is called a base die. One of the main benefits is controlling costs.
Smaller, faster chip manufacturing technology is always more expensive than slower, larger technology. Three-dimensional packaging lets chip designers use “tiles” made with pricier technology where it counts, such as for the brains of a computing chip, and then use older technology when speed is less critical, saving costs.
WHAT DOES INTEL’S TECHNOLOGY DO?
Multiple chipmakers, including Intel rival TSMC, have such three-dimensional packaging technology. What sets Intel’s packaging apart is that it can take in a wider variety of chiplets and meld them together without a loss of performance.
“You can take very small components now from a different factory – internal or external – and stick them into the package with much more fine granularity than you used to,” said Sanjay Natarajan, co-general manager of logic technology development at Intel.
Another of Intel’s technologies chiplets rest on top of copper columns, letting them suck up electricity more efficiently than other designs — an important feature for chips inside data centers, said David Kanter, an analyst with Real World Tech.
“Imagine you’ve got four small wires or one big fat piece of copper – that fat piece of copper is going to be better,” Kanter said.
WHY DOES PACKAGING MATTER TO INTEL’S BUSINESS?
Earlier this year, Intel announced plans to open its chip factories to outside customers to compete against TSMC. But wooing customers could take years because designers of complex chips such as Advanced Micro Devices Inc or Qualcomm Inc must work closely with their manufacturers, and switching is costly.
Offering packaging technologies to those customers lets Intel woo them, even if they still want to source important parts of their chips from Intel’s competitors.
“There’s a technology benefit, there’s a flexibility benefit and there’s a cost benefit,” said Ann B. Kelleher, general manager of technology development at Intel.
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